EN 
DE Armv8-A, Armv9-A: 64-bit Architekturen und deren Besonderheiten
Armv8-A, Armv9-A Architecture Overview Cortex AArch64 Processor Family Overview
- V8: Cortex-A32, -A35, -A53, -A55, -A57, -A72, -A73, -A75
- V9: Cortex-A520, -720, A320, Cortex-X4
- AArch64 Register Organization
- General Purpose, Special Purpose, System Control Registers
- Execution States
- Exception Levels
- Cortex-A 32-Bit Compatibility
- Loads and Stores
- Data Processing
- Flow Control
- Bit Manipulation
- Conditional Execution
- Scalar Floating Point and SIMD
- Data Barriers, Instruction Barriers
- Synchronization, Mutex, Semaphore
- Local and Global Exclusive Monitors
- OS Support
- Interrupts
- Synchronous Exceptions
- Asynchronous Exceptions
- System Errors
- Exception Handling in EL1
- Exceptions in EL2 and EL3
- GIC, Global Interrupt Controller Overview
- Memory Types and Access Permissions
- Shareability, Cacheability
- Alignment and Endianness
- Tagged Pointers
- Memory Management Unit, MMU
- Translation Look-aside Buffer, TLB
- TLB Maintenance Operations
- Translation Table Tree Organization
- Translation Levels
- Translation Table Entries, Attributes
- Translation at EL0/EL1
- Translation at EL2/EL3
- Stage 1 and Stage 2 Translation
- System MMU
- L1 and L2 Cache Operations and Organization
- Cache Maintenance Operations
- Cache Coherency in Singlecore and Multicore Systems
- Cache Coherent Interconnect Devices
- Arm Core Power Modes
- Power Control
- Arm Multicore Processor Power Modes
- Power State Coordination
- Debug Facilities and Features
- Trace Capabilities
- Performance Monitor Unit
- Activity Monitor Unit
- Booting a Multicore/Multiprocessor System
- Start-up, from Reset to main()
- Arm Virtualization Support for a Hypervisor
- Memory Management
- Virtual Exceptions
- Generic Timer – Virtual Timer
- Security Basics
- Trusted Base System Architecture (TBSA)
- Trusted Boot
- Trust Zone Controller
- Arm Confidential Compute Architecture (CCA)
- Realm Memory Extension (RME)
- Branch Target Identification (BTI)
- Memory Tagging Extension (MTE)
- Pointer Authentication (PA)
- Scalable Vector Extension (SVE2)
- Scalable Matrix Extension (SME)
- Arm®v9.2-A Debug Logic (TRBE, ETE, SPE, PMU, ELA)
- Sie erhalten Ihre Übungsverzeichnisse und Lösungsbeispiele für alle Übungsaufgaben.
AArch64 oder auch ARM64 ist die 64-Bit-Version der Core-Architekturfamilie von Arm. Sie wurde 2011 mit der Armv8-Architektur eingeführt und später in die Armv9 Version integriert und stellt aktuell die leistungsfähigste Core-Architektur von Arm dar. Genutzt wird sie in vielen Arm-Prozessoren, wie Cortex®-A32, -A35, -A53, -A55, -A57, -A72, -A73 und -A75 bis hin zu den Leistungsträgern Cortex®-A520, -A720 oder Cortex®-X4. Auch der neueste Vertreter von KI- (AI) und ultraeffizienten Prozessoren wie Cortex®-A320 nutzt die vielfältigen Erweiterungen von Armv9.
In diesem Training lernen Sie die Armv8-A und Armv9-A Architektur mit ihren Besonderheiten und Vorteilen kennen. Sie verstehen es, Mikrocontroller mit entsprechenden Kernen für Ihre Zwecke auszuwählen und effizient einzusetzen. Sie können C/C++ und Assembler-Programme erstellen, nutzen Safety- und Security-Mechanismen und haben den perfekten Einstieg in die Entwicklung Cortex® Armv8-A- bzw. Armv9-A-basierter Systeme.
IHRE VORTEILE:
Software- und Hardware-Entwickler, System-Architekten
Grundkenntnisse Mikrocontroller-Architekturen
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| Date | Location | Language | Price | Duration | |
|---|---|---|---|---|---|
*Price per participant, in Euro plus VAT.
Training code: AARCH64
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All inclusive!
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Lunch, soft drinks, tea and coffee, fruit, snacks,
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81737 Munich, Germany
+49 89 450617-71
>> Directions and hotel information
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Seminar location
MicroConsult Academy GmbH
Charles-de-Gaulle-Str. 6
81737 Munich, Germany
Phone: +49 89 450617-71 >> Directions
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Bonus program
The group advantage: Binding registration of a group for a training
Number of persons |
Amount of the discount |
| 2 to 3 people | 5 % |
| 4 to 5 people | 10 % |
| from 6 people | 15 % also when split into 2 dates |
| more than 8 people | upon request |
The training bonus: Binding registration of a person for several training courses
Number of training sessions |
Amount of the discount |
|---|---|
| 2 training sessions | 5 % |
| 3 training sessions | 8 % |
| More than 3 training sessions | upon request |
What else is important
This bonus scheme applies exclusively to our open training sessions.
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Please contact us, our Service Office is available at +49 (0)89 450617-71. Or you can also use the Contact form.
Together we will find the optimal solution for you!
Related trainings
Customer testimonials
Do need additional information? Feel free to get in touch!
Melanie Menzl
Organization open trainingsSilke Bluhm
Organization onsite trainings & coachingsNora Pohle
Saleskontakt@microconsult.com
+49 89 450617 - 71
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