Mikrocontroller
Arm®/CORTEX®
Armv8-A Architektur: AARCH64 Cortex®-A32, -A35, -A53, -A55, -A57, -A72, -A73, -A75 Präsenz-Training
Sie kennen die Architektur, Besonderheiten und Vorteile der Armv8-A (Application) Kernarchitektur.
Sie verstehen es, Mikrocontroller mit entsprechenden Kernen für Ihre Zwecke auszuwählen und effizient einzusetzen.
Sie können C/C++ und Assembler-Programme erstellen, nutzen Safety- und Security-Mechanismen und haben den perfekten Einstieg in die Entwicklung Cortex™ Armv8-A-basierter Systeme.
IHRE VORTEILE:
Effektiver und zeitsparender Einstieg in die Gesamtthematik
Praktische Tipps zu Multicore und Security
Übungen als Download
Umfangreiches Kompendium als Aufbereitung und für das Nachvollziehen des Gelernten auch nach dem Training.
Software- und Hardware-Entwickler, System-Architekten
Grundkenntnisse Mikrocontroller-Architekturen
Armv8-A Architecture Overview
Cortex AArch64 Processor Family Overview
- Cortex-A32, -A35, -A53, -A55, -A57, -A72, -A73, -A75
Cortex AArch64 Processor Core
- AArch64 Register Organization
- General Pupose, Special Purpose, System Control Registers
- Execution States
- Execution Levels
- Cortex-A 32 Bit Compatibility
Cortex AArch64 Instruction Set Architecture (ISA) Overview
- Loads and Stores
- Data Processing
- Flow Control
- Bit Manipulation
- Conditional Execution
- Scalar Floating-Point and SIMD
Barriers and Synchronization
- Data Barriers, Instruction Barriers
- Synchronization, Mutex, Semaphore
- Local and Global Exclusive Monitors
- OS Support
Cortex AArch64 Exception Model
- Interrupts
- Synchronous Exceptions
- Asynchronous Exceptions
- System Errors
- Exception Handling in EL1
- Exceptions in EL2 and EL3
- GIC, Global Interrupt Controller
Cortex AArch64 Memory Model
- Memory Types and Access Permissions
- Shareability, Cacheability
- Alignment and Endianess
- Tagged Pointers
Cortex AArch64 Memory Management
- Armv8-A Memory Management Unit, MMU
- Translation Look-aside Buffer, TLB
- TLB Maintenance Operations
- Translation Table Tree Organization
- Translation Levels
- Translation Table Entries, Attributes
- Translation at EL0/EL1
- Translation at EL2/EL3
- Stage 1 and Stage 2 Translation
- System MMU
Cortex AArch64 Caches
- L1 and L2 Cache Operations and Organization
- Cache Maintenance Operations
- Cache Coherency in Singlecore and Multicore Systems
- Cache Coherent Interconnect Devices
Cortex AArch64 Power Management
- ARM Core Power Modes
- Power Control
- ARM Multicore Processor Power Modes
- Power State Coordination
Cortex AArch64 Debug
- Debug Facilities
- Debug Features
- Trace
- Performance Monitor Unit
- Activity Monitor Unit
Cortex AArch64 Booting Singlecore/Multicore Systems
- Booting an AArch64 Core
- Booting a Multicore/Multiprocessor System
- Real-world Booting
- ARM Trusted Firmware
- Start-up, from Reset to main()
Cortex AArch64 Virtualization
- ARM Virtualization Support for a Hypervisor
- Memory Management
- Virtual Exceptions
- Generic Timer – Virtual Timer
Cortex AArch64 Security
- Security Basics
- Trusted Base System Architecture (TBSA)
- Trusted Boot
- Trust Zone Controller
Übungen
- Sie erhalten von uns Ihre Übungsverzeichnisse und Lösungsbeispiele für alle Übungsaufgaben.
Präsenz-Training
Onsite-Training
In maßgeschneiderten Workshops kombinieren wir Ihre konkreten Projektaufgaben mit unserem Trainingsangebot. Dabei berücksichtigen wir Ihre Anforderungen bezüglich Inhalt, Zeit, Ort, Dauer, technischem Umfeld und Vermittlungsmethodik.
Für Ihre Anfrage oder weiterführende Informationen stehen wir Ihnen gern zur Verfügung.
Live-Online - Deutsch
Coaching
Armv8-A Architektur: AARCH64 Cortex®-A32, -A35, -A53, -A55, -A57, -A72, -A73, -A75 Präsenz-Training
Inhalt
Armv8-A Architecture Overview
Cortex AArch64 Processor Family Overview
- Cortex-A32, -A35, -A53, -A55, -A57, -A72, -A73, -A75
Cortex AArch64 Processor Core
- AArch64 Register Organization
- General Pupose, Special Purpose, System Control Registers
- Execution States
- Execution Levels
- Cortex-A 32 Bit Compatibility
Cortex AArch64 Instruction Set Architecture (ISA) Overview
- Loads and Stores
- Data Processing
- Flow Control
- Bit Manipulation
- Conditional Execution
- Scalar Floating-Point and SIMD
Barriers and Synchronization
- Data Barriers, Instruction Barriers
- Synchronization, Mutex, Semaphore
- Local and Global Exclusive Monitors
- OS Support
Cortex AArch64 Exception Model
- Interrupts
- Synchronous Exceptions
- Asynchronous Exceptions
- System Errors
- Exception Handling in EL1
- Exceptions in EL2 and EL3
- GIC, Global Interrupt Controller
Cortex AArch64 Memory Model
- Memory Types and Access Permissions
- Shareability, Cacheability
- Alignment and Endianess
- Tagged Pointers
Cortex AArch64 Memory Management
- Armv8-A Memory Management Unit, MMU
- Translation Look-aside Buffer, TLB
- TLB Maintenance Operations
- Translation Table Tree Organization
- Translation Levels
- Translation Table Entries, Attributes
- Translation at EL0/EL1
- Translation at EL2/EL3
- Stage 1 and Stage 2 Translation
- System MMU
Cortex AArch64 Caches
- L1 and L2 Cache Operations and Organization
- Cache Maintenance Operations
- Cache Coherency in Singlecore and Multicore Systems
- Cache Coherent Interconnect Devices
Cortex AArch64 Power Management
- ARM Core Power Modes
- Power Control
- ARM Multicore Processor Power Modes
- Power State Coordination
Cortex AArch64 Debug
- Debug Facilities
- Debug Features
- Trace
- Performance Monitor Unit
- Activity Monitor Unit
Cortex AArch64 Booting Singlecore/Multicore Systems
- Booting an AArch64 Core
- Booting a Multicore/Multiprocessor System
- Real-world Booting
- ARM Trusted Firmware
- Start-up, from Reset to main()
Cortex AArch64 Virtualization
- ARM Virtualization Support for a Hypervisor
- Memory Management
- Virtual Exceptions
- Generic Timer – Virtual Timer
Cortex AArch64 Security
- Security Basics
- Trusted Base System Architecture (TBSA)
- Trusted Boot
- Trust Zone Controller
Übungen
- Sie erhalten von uns Ihre Übungsverzeichnisse und Lösungsbeispiele für alle Übungsaufgaben.