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AURIX™ TC2xx Workshop: 32-Bit Multicore Microcontroller Family

  • Content
     
  • Objectives
  • Participants
  • Requirements

You know the architecture, on-chip peripherals and features (especially of the multicore architecture and safety extensions) of the AURIX™ family. You are able to program low-level drivers for this hardware and test them with a debugger. You can moreover generate interrupt and trap routines.

Hardware and software architects, hardware and software developers, test engineers

Knowledge of ANSI-C as well as experience with programming and the set-up of a microprocessor/microcontroller system.

Infineon AURIX™Architecture: Overview

AURIX™ Multicore

  • CPU, pipelines, register sets, floating point unit FPU, DSP support
  • Memory model, local and global memory units
  • On-chip bus systems: 64-bit XBAR, 32-bit system peripheral bus SPB

Protection System

Multicore Interrupt Processing: Interrupt Router and TRAP System

Direct Memory Access Controller DMA

Timer

  • System timer module STM
  • Generic timer module GTM
  • Capture and compare unit CCU6

Communication Interfaces

  • UART/LIN, QSPI, I2C, MSC, HSSL & HSCT
  • Overview: MultiCAN, Ethernet, FlexRay®

Sensor Interfaces

  • Single edge nibble transmission SENT
  • Peripheral sensor interface PSI5

Analog-to-Digital Converter

  • Versatile analog-digital converter VADC
  • Delta-sigma analog-digital converter DSADC

System Control Unit SCU

  • Clock control
  • Resets
  • Power management
  • External request unit ERU
  • Start-up process
  • Watchdog timer WDT

Safety

On-chip Debug System OCDS

Overview: Emulation Device & Calibration

Exercises

  • Exercises are performed with an Infneon AURIX™ board, focusing on the aspects interrupt controller, DMA controller, multicore start-up, peripheral initialization.


The price includes lunch,

drinks, training documentation and certificate.


Information for HR

You can book up to 5 participants on one training with our online order form.
If you wish to book more participants on several trainings, please contact us!
Please also note our bonus program when booking several trainings and/or participants at once.


Information for HR

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Training Code: E-TC17XXPER

Embedded C Training: Programming Methods and Tools for Embedded Applications
Training Code: E-EMB-C

Embedded C++: Object-oriented Programming for Microcontrollers with C++/EC++ and UML
Training Code: E-EC++

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Training Code: E-µC-MULTI


Related trainings

Trainings

DatePrice *Duration
22.01. – 26.01.20182.750,00 €5 days 
19.03. – 23.03.20182.750,00 €5 days 
04.06. – 08.06.20182.750,00 €5 days 
17.09. – 21.09.20182.750,00 €5 days 
21.01. – 25.01.20192.750,00 €5 days 
Training code: E-AURIX
* All prices are exclusive of applicable VAT.


> Registration form download (PDF)
> Training details as PDF

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> Training details as PDF

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AURIX™ TC2xx Workshop: 32-Bit Multicore Microcontroller Family

Content

Infineon AURIX™Architecture: Overview

AURIX™ Multicore

  • CPU, pipelines, register sets, floating point unit FPU, DSP support
  • Memory model, local and global memory units
  • On-chip bus systems: 64-bit XBAR, 32-bit system peripheral bus SPB

Protection System

Multicore Interrupt Processing: Interrupt Router and TRAP System

Direct Memory Access Controller DMA

Timer

  • System timer module STM
  • Generic timer module GTM
  • Capture and compare unit CCU6

Communication Interfaces

  • UART/LIN, QSPI, I2C, MSC, HSSL & HSCT
  • Overview: MultiCAN, Ethernet, FlexRay®

Sensor Interfaces

  • Single edge nibble transmission SENT
  • Peripheral sensor interface PSI5

Analog-to-Digital Converter

  • Versatile analog-digital converter VADC
  • Delta-sigma analog-digital converter DSADC

System Control Unit SCU

  • Clock control
  • Resets
  • Power management
  • External request unit ERU
  • Start-up process
  • Watchdog timer WDT

Safety

On-chip Debug System OCDS

Overview: Emulation Device & Calibration

Exercises

  • Exercises are performed with an Infneon AURIX™ board, focusing on the aspects interrupt controller, DMA controller, multicore start-up, peripheral initialization.

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