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AURIX™ TC4xx Crash Course: 32-Bit Multicore Microcontroller Family (Aurix-3G Third Generation) - Face-to-Face Training

  • Content
     
  • Objectives
     
  • Participants
     
  • Requirements
     

You know the architecture and particularly the innovations and features (multicore and safety extensions) of the latest generation of the AURIX™ device family.

You can efficiently adapt your software architectures to hardware, thus developing high-performance systems.

The compact training format enables you to quickly implement your new knowledge in your projects.

YOUR BENEFIT:

Efficient and compact jump-start into the overall topic (saves three months according to our customers)

Practical tips on multicore and safety

Integrators, architects, developers, test engineers, those switching to or starting to work with AURIX™

Experience in microcontroller/microprocessor system programming and architecture. Knowledge of earlier AURIX generations is an advantage but not a requirement.

Introduction

  • History
  • Markets and applications
  • Key differentiators
  • Main building blocks

System Architecture

  • Block diagrams
  • Clustering und accelerators
  • Main CPU subsystems
  • Memory architecture
  • Buses
  • Conclusions for software architecture

Infrastructure

  • Crossbars
  • Peripheral buses
  • Bridges

Virtualization

  • Use cases
  • Implementation patterns

TriCore™ CPU Subsystems

  • Core architecture
  • Block diagram
  • Pipelines
  • Core specific function registers
  • Register files and context switching
  • Specific instructions and spinlock example
  • Extensions for virtualization
  • Trap system
  • Memory protection unit (MPU)
  • System timer (STM)

Protection Mechanisms

  • PROT
  • Access protection unit (APU)

Interrupt Router

  • Configuration
  • Software trigger
  • Broadcasting
  • External Interrupts

System Control and Management

  • Clocking
  • Non maskable interrupts (NMI)
  • Reset
  • External service request pins (ESR)
  • System modes
  • Booting

Safety Concept

  • Measures
  • Safety and security management unit (SMU)

Security Concept

  • Cybersecurity real-time module (CSRM)
  • Cybersecurity satellite

Debug and Trace Aspects

  • New internal architecture
  • SMP vs. AMP debug

IMPORTANT NOTE:

  • A valid NDA with the chip vendor is a pre-requirement to attend the Aurix-3G crash course.


CONTACT

Melanie Menzl
Phone +49 (0)89 450617-71


SEMINAR LOCATION


ORGANIZATIONAL DETAILS

The training price includes:
Lunch, drinks, training documentation and your training certificate.


ALL INCLUSIVE!


BONUS SCHEDULE

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Coaching: TriCore™/AURIX™
Training code: C-TRI-AUR


Related trainings

FACE-TO-FACE TRAINING

DatePrice *Duration
10.02. – 12.02.20251.875,00 €2.5 days 
Training code: E-A3GCRSH
* Price per attendee, in Euro plus VAT
> Registration form download (PDF)> Training details as PDF

Onsite Training

Our customized workshops integrate your specific project tasks in our training content and accommodate your requirements on content, time, location, duration, technical environment and knowledge transfer methodology.

Please contact us for further information or an individual quotation.

> Training details as PDF

Live Online - English

Date Duration
07.04. – 09.04.2025 2.5 days  

Face-To-Face - German

Date Duration
10.02. – 12.02.2025 2.5 days  

Live Online - German

Date Duration
07.04. – 09.04.2025 2.5 days  

Coaching

Our coaching services offer a major advantage: our specialists introduce their expertise and experience directly in your solution process, thus contributing to the success of your projects.

Coaching: TriCore™/AURIX™

AURIX™ TC4xx Crash Course: 32-Bit Multicore Microcontroller Family (Aurix-3G Third Generation) - Face-to-Face Training

Content

Introduction

  • History
  • Markets and applications
  • Key differentiators
  • Main building blocks

System Architecture

  • Block diagrams
  • Clustering und accelerators
  • Main CPU subsystems
  • Memory architecture
  • Buses
  • Conclusions for software architecture

Infrastructure

  • Crossbars
  • Peripheral buses
  • Bridges

Virtualization

  • Use cases
  • Implementation patterns

TriCore™ CPU Subsystems

  • Core architecture
  • Block diagram
  • Pipelines
  • Core specific function registers
  • Register files and context switching
  • Specific instructions and spinlock example
  • Extensions for virtualization
  • Trap system
  • Memory protection unit (MPU)
  • System timer (STM)

Protection Mechanisms

  • PROT
  • Access protection unit (APU)

Interrupt Router

  • Configuration
  • Software trigger
  • Broadcasting
  • External Interrupts

System Control and Management

  • Clocking
  • Non maskable interrupts (NMI)
  • Reset
  • External service request pins (ESR)
  • System modes
  • Booting

Safety Concept

  • Measures
  • Safety and security management unit (SMU)

Security Concept

  • Cybersecurity real-time module (CSRM)
  • Cybersecurity satellite

Debug and Trace Aspects

  • New internal architecture
  • SMP vs. AMP debug

IMPORTANT NOTE:

  • A valid NDA with the chip vendor is a pre-requirement to attend the Aurix-3G crash course.