AURIX™ TC3xx Workshop: 32-Bit Multicore Microcontroller Family (Aurix-2G Second Generation) - Face-to-Face Training
You know the architecture, basic on-chip peripherals and the features (especially related to multicore and safety extensions) of the AURIX™ device family.
You get to apply low-level drivers for this hardware, adapt examples as required and test them with a debugger.
Numerous exercises make this training a practice-oriented software workshop.
Efficient and compact jump-start into the overall topic
Practical tips on multicore and safety
Exercises on USB stick or as download.
Hardware and software architects, hardware and software developers, test engineers // IMPORTANT NOTE: A valid NDA with the chip vendor is a pre-requirement to attend the Aurix-2G training course.
ANSI-C knowledge; experience in microcontroller/microprocessor system programming and architecture
Infineon AURIX™ 2G Architecture
- Multicore architectural blocks
- Consequences for software architectures
- Multicore instruction set extensions
- Registers files and context switching
- Memory protection unit (software monitoring)
- Crossbar and peripheral bus
- CPU clustering
- Performance aspects for software
- Memory map
- Configuration options
- Cache and software handling
Infineon Low-Level Drivers: Overview
- Configuration structures
- Application programming interface
- Library distribution
- Frameworks and demos
Exceptions and Handling
- Traps (hardware and software)
- Interrupts (hardware and software)
- Vector tables
- Broadcast software interrupts (core synchronization)
- External interrupts
Direct Memory Access Controller DMA
- Move engines
- Triggering (hardware and software)
- Advanced features (software relaxation)
- System timer (STM)
- General purpose timer 12 (GPT12)
- Capture compare unit (CCU)
- Watchdog timer (WDT)
- Temporal protection timer (TPS, exception timer)
- Generic timer module (GTM) - overview
Safety and Security
- Safety measures
- Safety management unit (SMU)
- Protection mechanisms
- IO monitoring
- Hardware security module (HSM) - implementation overview
- Startup and boost
- Low power options
- Communication and synchronization
- Intrinsics usage in C/C++
- Tool aspects (compiler, linker)
- Debugging (AMP, SMP)
- Reset: sources, types and consequences
- Boot: software configuration and modes
- Emergency stop requests
Power Management System (PMS)
- Supply generation options
- Embedded voltage regulators
- Standby and wakeup
- Die temperature sensor
Synchronous and Asynchronous Standard Peripherals
- Micro second channel (MSC)
- Serial peripheral interface (QSPI)
- Inter IC interface (I2C)
- UART (ASCLIN)
Analog To Digital Converter
- Enhanced features offloading software
Automotive Interfaces: Overview
High Speed Serial Link Interface (HSSL)
- Multicore aspects
- Numerous exercises will be conducted on an Infineon AURIX™ board, covering the following aspects: use of low-level drivers, protection mechanisms, interrupt controller, DMA controller, system timer, port, multicore aspects, monitoring, performance measurement etc.
IMPORTANT NOTE: A valid NDA with the chip vendor is a pre-requirement to attend the Aurix-2G training course.
Please note that the Aurix-2G training does not explicitly cover ADAS specific blocks. If required, please contact our service office prior to the training, phone +49 (0)89 450617-71.
|3.500,00 €||5 days|
|Training code: E-AURIX2G|
* Price per attendee, in Euro plus VAT
Our customized workshops integrate your specific project tasks in our training content and accommodate your requirements on content, time, location, duration, technical environment and knowledge transfer methodology.
Please contact us for further information or an individual quotation.
Live Online - English
Face-To-Face - German
|27.11. – 01.12.2023||5 days|
Live Online - German
|11.09. – 15.09.2023||5 days|
|26.02. – 01.03.2024||5 days|
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