Experience Embedded

Professional Training, Consulting and Project Support

AURIX™ TC3xx Workshop: 32-Bit Multicore Microcontroller Family (2G Second Generation) - Live Online Training

  • Content
     
  • Objectives
     
  • Participants
     
  • Requirements
     

You know the architecture, basic on-chip peripherals and the features (especially related to multicore and safety extensions) of the AURIX™ device family.

You get to apply low-level drivers for this hardware, adapt examples as required and test them with a debugger.

Numerous exercises make this training a practical software workshop.

YOUR BENEFIT:

Efficient and compact jump-start into the overall topic

Practical tips on multicore and safety

Exercises on USB stick or as download.

Hardware and software architects, hardware and software developers, test engineers // IMPORTANT NOTE: A valid NDA with the chip vendor is a pre-requirement to attend the course.

ANSI-C knowledge; experience in microcontroller/microprocessor system programming and architecture

Infineon AURIX™ 2G Architecture

  • Multicore architectural blocks
  • Interconnectivity
  • Consequences for software architectures

CPU Subsystem

  • Multicore instruction set extensions
  • Registers files and context switching
  • Memory protection unit (software monitoring)

Internal Connectivity

  • Crossbar and peripheral bus
  • CPU clustering
  • Performance aspects for software

Memory

  • Memory map
  • Configuration options
  • Cache and software handling
  • Types
  • Hierarchy
  • Test

Infineon Low-Level Drivers: Overview

  • Configuration structures
  • Application programming interface
  • Library distribution
  • Frameworks and demos

Ports

Exceptions and Handling

  • Traps (hardware and software)
  • Interrupts (hardware and software)
  • Vector tables
  • Broadcast software interrupts (core synchronization)
  • External interrupts

Direct Memory Access Controller DMA

  • Move engines
  • Triggering (hardware and software)
  • Advanced features (software relaxation)

Timer

  • System timer (STM)
  • General purpose timer 12 (GPT12)
  • Capture compare unit (CCU)
  • Watchdog timer (WDT)
  • Temporal protection timer (TPS, exception timer)
  • Generic timer module (GTM) - overview

Safety and Security

  • Safety measures
  • Safety management unit (SMU)
  • Protection mechanisms
  • IO monitoring
  • Hardware security module - implementation overview

Multicore Aspects

  • Startup and boost
  • Low power options
  • Communication and synchronization
  • Intrinsics usage in C/C++
  • Tool apsects (compiler, linker)
  • Debugging (AMP, SMP)

System Control

  • Reset: sources, types and consequences
  • Boot: software configuration and modes
  • Clocking
  • Emergency stop requests

Power Management System (PMS)

  • Supply generation options
  • Embedded voltage regulators
  • Standby and wakeup
  • Die temperature sensor

Synchronous and Asynchronous Standard Peripherals

  • Micro second channel (MSC)
  • Serial peripheral interface (QSPI)
  • Inter IC interface (I2C)
  • UART (ASCLIN)

Sensor Interfaces

  • SENT
  • PSI5
  • PSI5-S

Analog To Digital Converter

  • EVADC
  • EDSADC
  • Enhanced features offloading software

Automotive Interfaces: Overview

  • LIN
  • CAN
  • FlexRay®

High Speed Serial Link Interface (HSSL)

Ethernet: Overview/Demo

Debug

  • Interfaces
  • Tracing
  • Multicore aspects

Exercises

  • Numerous exercises will be conducted on an Infineon AURIX™ board, covering the following aspects: use of low-level drivers, protection mechanisms, interrupt controller, DMA controller, system timer, port, multicore aspects, monitoring, performance measurement etc.

--------------------------------------------------------------------------

IMPORTANT NOTE: A valid NDA with the chip vendor is a pre-requirement to attend the course.

-------------------------------------------------------------------------

Please note that this training does not explicitly cover ADAS specific blocks. If required, please contact our service office prior to the training, phone +49 (0)89 450617-71.

The training price includes:
Training documentation, your training certificate and target HW etc. where required.


ALL INCLUSIVE!

We will send you a binding confirmation if the training takes place, at the latest, 3 weeks before the training starts.

Several days before the Live Online Training, you will get e-mails with …

  • detailed information regarding your training
  • your training documents (download link)
  • an invitation to an optional test session with your trainer
  • an invitation for the training days, with link and access data

Any target HW that might be required for the training will be shipped to you in advance.


PROCEDURE

Live-Online-Training

Date Price *Duration
04.10. – 08.10.20213.250,00 €5 Days 
06.12. – 10.12.20213.250,00 €5 Days 
Training code: LE-AURIX2G
* Price per attendee, in Euro plus VAT


> Registration form download (PDF)
> Training details as PDF

Face-To-Face - English

Date Duration
04.10. – 08.10.2021 5 days  
06.12. – 10.12.2021 5 days  
07.02. – 11.02.2022 5 days  

Live Online - German

Date Duration
03.05. – 07.05.2021 5 days  
19.07. – 23.07.2021 5 days  
04.10. – 08.10.2021 5 days  
06.12. – 10.12.2021 5 days  

Face-To-Face - German

Date Duration
19.07. – 23.07.2021 5 days  
04.10. – 08.10.2021 5 days  
06.12. – 10.12.2021 5 days  
07.02. – 11.02.2022 5 days  

AURIX™ TC3xx Workshop: 32-Bit Multicore Microcontroller Family (2G Second Generation) - Live Online Training

Content

Infineon AURIX™ 2G Architecture

  • Multicore architectural blocks
  • Interconnectivity
  • Consequences for software architectures

CPU Subsystem

  • Multicore instruction set extensions
  • Registers files and context switching
  • Memory protection unit (software monitoring)

Internal Connectivity

  • Crossbar and peripheral bus
  • CPU clustering
  • Performance aspects for software

Memory

  • Memory map
  • Configuration options
  • Cache and software handling
  • Types
  • Hierarchy
  • Test

Infineon Low-Level Drivers: Overview

  • Configuration structures
  • Application programming interface
  • Library distribution
  • Frameworks and demos

Ports

Exceptions and Handling

  • Traps (hardware and software)
  • Interrupts (hardware and software)
  • Vector tables
  • Broadcast software interrupts (core synchronization)
  • External interrupts

Direct Memory Access Controller DMA

  • Move engines
  • Triggering (hardware and software)
  • Advanced features (software relaxation)

Timer

  • System timer (STM)
  • General purpose timer 12 (GPT12)
  • Capture compare unit (CCU)
  • Watchdog timer (WDT)
  • Temporal protection timer (TPS, exception timer)
  • Generic timer module (GTM) - overview

Safety and Security

  • Safety measures
  • Safety management unit (SMU)
  • Protection mechanisms
  • IO monitoring
  • Hardware security module - implementation overview

Multicore Aspects

  • Startup and boost
  • Low power options
  • Communication and synchronization
  • Intrinsics usage in C/C++
  • Tool apsects (compiler, linker)
  • Debugging (AMP, SMP)

System Control

  • Reset: sources, types and consequences
  • Boot: software configuration and modes
  • Clocking
  • Emergency stop requests

Power Management System (PMS)

  • Supply generation options
  • Embedded voltage regulators
  • Standby and wakeup
  • Die temperature sensor

Synchronous and Asynchronous Standard Peripherals

  • Micro second channel (MSC)
  • Serial peripheral interface (QSPI)
  • Inter IC interface (I2C)
  • UART (ASCLIN)

Sensor Interfaces

  • SENT
  • PSI5
  • PSI5-S

Analog To Digital Converter

  • EVADC
  • EDSADC
  • Enhanced features offloading software

Automotive Interfaces: Overview

  • LIN
  • CAN
  • FlexRay®

High Speed Serial Link Interface (HSSL)

Ethernet: Overview/Demo

Debug

  • Interfaces
  • Tracing
  • Multicore aspects

Exercises

  • Numerous exercises will be conducted on an Infineon AURIX™ board, covering the following aspects: use of low-level drivers, protection mechanisms, interrupt controller, DMA controller, system timer, port, multicore aspects, monitoring, performance measurement etc.

--------------------------------------------------------------------------

IMPORTANT NOTE: A valid NDA with the chip vendor is a pre-requirement to attend the course.

-------------------------------------------------------------------------

Please note that this training does not explicitly cover ADAS specific blocks. If required, please contact our service office prior to the training, phone +49 (0)89 450617-71.