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Cortex®-R4, R5, R7, R8: Arm® Cortex-R Architecture Training

  • Content
     
  • Objectives
     
  • Participants
     
  • Requirements
     

You know the Cortex® R4, R5, R7 and R8 architecture and can write software in C and Assembler. You can place the programs in memory and test them. You get the perfect introduction in developing Cortexbased systems.

Software and hardware developers. If you already attended our Training "Arm7/9/10/11: Architecture and Embedded Programming", please contact us prior to booking.

A basic understanding of ANSI-C and microcontrollers.

Arm Cortex Processor Architecture

  • Register organization, operation modes, states, pipeline

Arm Processor Cores - Overview

  • Cortex®-R4, -R5, -R7, -R8 processor core
  • Cortex®-Av7, Cortex™-Av8 processor cores
  • Cortex®-Mv7, Cortex®-Mv8 processor cores
  • Arm7/9/11 processor core

Arm, Thumb, Thumb-2 Instruction Sets

  • Arm v4, v4T, v5, v6 instruction set
  • Thumb instruction set
  • v7 Thumb-2 instruction set
  • Data barriers, instruction barriers
  • Synchronization, load/store exclusice instructions
  • ARM/Thumb interworking
  • Assembler directives

Exception Handling

  • FIQ, IRQ, abort, supervisor call, undefined
  • Exception handler examples
  • Vectored interrupt controller, VIC
  • Generic interrupt controller, GIC

Coprocessors, Floating Point Unit

  • Arm coprocessor concept
  • System controller CP15
  • Floating point unit, FPU
  • System configuration

L1 Memory Interface

  • Tightly coupled memory, cache architecture
  • Memory protection unit, MPU

L2 Memory Interface

  • Advanced microprocessor bus architecture - AXI
  • Master interface
  • Slave interface

Debug, Trace, Performance Monitoring

  • Watchpoint units, embedded trace macrocell ETM
  • Performance monitor unit, PMU

Multi-Processing Features

  • Private memory region
  • Snoop control unit, SCU
  • Hardware coherency management
  • Split mode (performance mode)
  • Locked mode (safety mode)

Power Modes

  • Run, standby, dormant, shutdown

Embedded Software Development

  • Adjustment of library routines to hardware (retargeting)
  • Placing code and data in memory (scatter loading)
  • Linker description file
  • Reset, start-up, start-up file
  • From reset to main

Efficient C programming for Cortex architectures

  • Compiler optimization, compiler options
  • Interface C - Assembler
  • Programming guidelines for Arm compilers
  • Optimized utilization of local and global data

Hardware-near C

  • C statements and their execution in Assembler
  • Access to peripherals in C
  • Layer model for embedded systems
  • Structured description of peripherals

Practical Exercises with Keil µVision and Arm RealView Tools

  • Different tools can be used on request
  • All programs are tested on an evaluation board

The training price includes:
Lunch, drinks, training documentation and your training certificate.


ALL INCLUSIVE!



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Related trainings

Trainings

DatePrice *Duration
25.11. – 28.11.20192.400,00 €4 days 
20.04. – 23.04.20202.400,00 €4 days 
Training code: E-CORTEXR4
* Price per attendee, in Euro plus VAT


> Registration form download (PDF)
> Training details as PDF

Onsite Training

Our customized workshops integrate your specific project tasks in our training content and accommodate your requirements on content, time, location, duration, technical environment and knowledge transfer methodology.

Please contact us for further information or an individual quotation.

> Training details as PDF

Coaching

Our coaching services offer a major advantage: our specialists introduce their expertise and experience directly in your solution process, thus contributing to the success of your projects.

Coaching: Arm®/CORTEX®

Cortex®-R4, R5, R7, R8: Arm® Cortex-R Architecture Training

Content

Arm Cortex Processor Architecture

  • Register organization, operation modes, states, pipeline

Arm Processor Cores - Overview

  • Cortex®-R4, -R5, -R7, -R8 processor core
  • Cortex®-Av7, Cortex™-Av8 processor cores
  • Cortex®-Mv7, Cortex®-Mv8 processor cores
  • Arm7/9/11 processor core

Arm, Thumb, Thumb-2 Instruction Sets

  • Arm v4, v4T, v5, v6 instruction set
  • Thumb instruction set
  • v7 Thumb-2 instruction set
  • Data barriers, instruction barriers
  • Synchronization, load/store exclusice instructions
  • ARM/Thumb interworking
  • Assembler directives

Exception Handling

  • FIQ, IRQ, abort, supervisor call, undefined
  • Exception handler examples
  • Vectored interrupt controller, VIC
  • Generic interrupt controller, GIC

Coprocessors, Floating Point Unit

  • Arm coprocessor concept
  • System controller CP15
  • Floating point unit, FPU
  • System configuration

L1 Memory Interface

  • Tightly coupled memory, cache architecture
  • Memory protection unit, MPU

L2 Memory Interface

  • Advanced microprocessor bus architecture - AXI
  • Master interface
  • Slave interface

Debug, Trace, Performance Monitoring

  • Watchpoint units, embedded trace macrocell ETM
  • Performance monitor unit, PMU

Multi-Processing Features

  • Private memory region
  • Snoop control unit, SCU
  • Hardware coherency management
  • Split mode (performance mode)
  • Locked mode (safety mode)

Power Modes

  • Run, standby, dormant, shutdown

Embedded Software Development

  • Adjustment of library routines to hardware (retargeting)
  • Placing code and data in memory (scatter loading)
  • Linker description file
  • Reset, start-up, start-up file
  • From reset to main

Efficient C programming for Cortex architectures

  • Compiler optimization, compiler options
  • Interface C - Assembler
  • Programming guidelines for Arm compilers
  • Optimized utilization of local and global data

Hardware-near C

  • C statements and their execution in Assembler
  • Access to peripherals in C
  • Layer model for embedded systems
  • Structured description of peripherals

Practical Exercises with Keil µVision and Arm RealView Tools

  • Different tools can be used on request
  • All programs are tested on an evaluation board

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