Microcontrollers
TriCore™/AURIX™
AURIX™ TC4xx: 32-Bit Multicore Microcontroller Family (Aurix-3G Third Generation) - Live Online Training
You know the architecture, basic on-chip peripherals and the features (especially related to multicore and safety extensions) of the AURIX™ device family.
You get to apply low-level drivers for this hardware, adapt examples as required and test them with a debugger.
Numerous exercises make this training a practice-oriented software workshop.
YOUR BENEFIT:
Efficient and compact jump-start into the overall topic
Practical tips on multicore and safety
Exercises for download
Hardware and software architects, hardware and software developers, test engineers // IMPORTANT NOTE: A valid NDA with the chip vendor is a pre-requirement to attend the Aurix-3G training course.
ANSI-C knowledge; experience in microcontroller/microprocessor system programming and architecture
Introduction
System Architecture
Internal Infrastructure
- SRI
- FPI
- LLI
Virtual Machines and Hypervisor
TriCore™ CPU
- Context Switching
- New instructions
- Virtualisation
- Trap system
- MPU
- System timer
Protection Mechanisms
- PROT
- APU
Memory
- NVM
- UCBs
- SOTA
- Cache
Ports
Interrupt Router (IR)
System Direct Memory Access Controller
Safety Concept
- CRC engine
- Watch dogs
- BIST
- Clocking
- Voltage monitors
- SMU
Security Concept
- CS Real-time module
- CS Satellite
Power Management System
- Domains
- Wakup timer
- RTC
- Standby Controller
System Control and Management
- Clocking
- NMI
- Reset
- Firmware
- Boot
Complex Peripherals Overview and Special Features
- PPU
- GTM
- CAN
- xSPI
- PCIe
- ETH
Data Routing Engine
Analog to Digital Conversion
- TMADC
- Fast Compare
- DSADC
- CDSP
Multicore Debug
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IMPORTANT NOTE: A valid NDA with the chip vendor is a pre-requirement to attend the Aurix-3G training course.
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Please note that the Aurix-3G training does not explicitly cover ADAS specific blocks. If required, please contact our service office prior to the training, phone +49 (0)89 450617-71.
Face-To-Face - English
Live Online - German
Face-To-Face - German
AURIX™ TC4xx: 32-Bit Multicore Microcontroller Family (Aurix-3G Third Generation) - Live Online Training
Content
Introduction
System Architecture
Internal Infrastructure
- SRI
- FPI
- LLI
Virtual Machines and Hypervisor
TriCore™ CPU
- Context Switching
- New instructions
- Virtualisation
- Trap system
- MPU
- System timer
Protection Mechanisms
- PROT
- APU
Memory
- NVM
- UCBs
- SOTA
- Cache
Ports
Interrupt Router (IR)
System Direct Memory Access Controller
Safety Concept
- CRC engine
- Watch dogs
- BIST
- Clocking
- Voltage monitors
- SMU
Security Concept
- CS Real-time module
- CS Satellite
Power Management System
- Domains
- Wakup timer
- RTC
- Standby Controller
System Control and Management
- Clocking
- NMI
- Reset
- Firmware
- Boot
Complex Peripherals Overview and Special Features
- PPU
- GTM
- CAN
- xSPI
- PCIe
- ETH
Data Routing Engine
Analog to Digital Conversion
- TMADC
- Fast Compare
- DSADC
- CDSP