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AURIX™ TC3xx Workshop: 32-Bit Multicore Microcontroller Family (2G Second Generation)

  • Content
     
  • Objectives
  • Participants
  • Requirements

You know the architecture, basic on-chip peripherals and the key differentiators (especially multicore and functional safety) of the AURIX device family. You get to apply low-level drivers and test examples with a debugger.-----------------------------------------------------------------------------------Your advantage: Efficient and compact jump-start into the overall topic Practical tips and tricks related to Multicore and Safety Exercises on USB-stick or downloadable

Hardware- and Software-Architects, Hardware- and Software-Developers, Testengineers

ANSI-C knowledge; experience in programming and architecture of microcontrollers

Infineon AURIX™ 2G Architecture

CPU Subsystem

Internal Connectivity

Memory

  • Types
  • Hierarchy
  • Test

Low Level Drivers: Overview

Ports

Exceptions and Handling

Direct Memory Access Controller DMA

Timer

  • System Timer (STM)
  • General Purpose Timer 12 (GPT12)
  • Capture Compare Unit (CCU)
  • Watch Dog Timer (WDT)
  • Temporal Protection Timer (TPS, Exception Timer)
  • Generic Timer Module (GTM): Overview

Safety and Security

  • Safety Measures
  • Safety Management Unit (SMU)
  • Protection

Multicore Aspects

System Control

  • Reset
  • Boot
  • Clocking

Power Management System (PMS)

Synchronous and Asynchronous

Standard Peripherals

  • Micro Second Channel (MSC)
  • Serial Peripheral Interface (QSPI)
  • Inter IC Interface (I2C)
  • UART (ASCLIN)

Sensor Interfaces

  • SENT
  • PSI5
  • PSI5-S

Analog To Digital Converter

  • EVADC
  • EDSADC

Automotive Interfaces: Overview

  • LIN
  • CAN
  • FlexRay®

High Speed Serial Link Interface (HSSL)

Ethernet: Overview

Debug

Execrises

  • Exercises will be conducted on an Infineon AURIX™ Board to cover the following aspects: Usage of Low Level Drivers, Protection, Interrupt Controller, DMA Controller, System Timer, Port, Multicore aspects

---------------------------------------------------------------------------------

IMPORTANT NOTE: An active NDA with the chip vendor is a pre-requirement to attend the course.


The price includes lunch,

drinks, training documentation and certificate.


Information for HR

You can book up to 5 participants on one training with our online order form.
If you wish to book more participants on several trainings, please contact us!
Please also note our bonus program when booking several trainings and/or participants at once.


Information for HR

Related trainings

Generic Timer Module (Bosch-GTM): Architecture and Programming
Training Code: E-GTM

Debugging with the PLS Universal Debug Engine UDE
Training Code: E-UDE-PLS

Tracing and Multicore Debugging with the PLS Universal Debug Engine UDE
Training Code: E-MCDS-PLS

Debugging for TriCore/AURIX™ with Lauterbach TRACE32
Training Code: E-T32-BASE

Embedded C Training: Programming Methods and Tools for Embedded Applications
Training Code: E-EMB-C

Embedded C++: Object-oriented Programming for Microcontrollers with C++/EC++ and UML
Training Code: E-EC++

Software Architecture Training for Embedded Systems and Real-time Systems
Training Code: E-EMB-ARCH

Embedded Multicore Microcontrollers: Practical Application
Training Code: E-µC-MULTI


Related trainings

Trainings

DatePrice *Duration
20.11. – 24.11.20172.750,00 €5 days 
22.01. – 26.01.20182.750,00 €5 days 
19.03. – 23.03.20182.750,00 €5 days 
04.06. – 08.06.20182.750,00 €4.5 days 
10.09. – 14.09.20182.750,00 €5 days 
26.11. – 30.11.20182.750,00 €5 days 
04.02. – 08.02.20192.750,00 €5 days 
Training code: E-AURIX-2G
* All prices are exclusive of applicable VAT.


> Registration form download (PDF)
> Training details as PDF

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In customized workshops, we integrate your specific project tasks and our training program, considering your requirements as regards content, time, location, duration, technical environment and knowledge transfer methodology.

Please contact us for further information or an individual quotation.

> Training details as PDF

Coaching

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AURIX™ TC3xx Workshop: 32-Bit Multicore Microcontroller Family (2G Second Generation)

Content

Infineon AURIX™ 2G Architecture

CPU Subsystem

Internal Connectivity

Memory

  • Types
  • Hierarchy
  • Test

Low Level Drivers: Overview

Ports

Exceptions and Handling

Direct Memory Access Controller DMA

Timer

  • System Timer (STM)
  • General Purpose Timer 12 (GPT12)
  • Capture Compare Unit (CCU)
  • Watch Dog Timer (WDT)
  • Temporal Protection Timer (TPS, Exception Timer)
  • Generic Timer Module (GTM): Overview

Safety and Security

  • Safety Measures
  • Safety Management Unit (SMU)
  • Protection

Multicore Aspects

System Control

  • Reset
  • Boot
  • Clocking

Power Management System (PMS)

Synchronous and Asynchronous

Standard Peripherals

  • Micro Second Channel (MSC)
  • Serial Peripheral Interface (QSPI)
  • Inter IC Interface (I2C)
  • UART (ASCLIN)

Sensor Interfaces

  • SENT
  • PSI5
  • PSI5-S

Analog To Digital Converter

  • EVADC
  • EDSADC

Automotive Interfaces: Overview

  • LIN
  • CAN
  • FlexRay®

High Speed Serial Link Interface (HSSL)

Ethernet: Overview

Debug

Execrises

  • Exercises will be conducted on an Infineon AURIX™ Board to cover the following aspects: Usage of Low Level Drivers, Protection, Interrupt Controller, DMA Controller, System Timer, Port, Multicore aspects

---------------------------------------------------------------------------------

IMPORTANT NOTE: An active NDA with the chip vendor is a pre-requirement to attend the course.

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