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AURIX™ TC3xx Workshop: 32-Bit Multicore Microcontroller Family (2G Second Generation)

  • Content
     
  • Objectives
     
  • Participants
     
  • Requirements
     

You know the architecture, basic on-chip peripherals and the features (especially related to multicore and safety extensions) of the AURIX™ device family. You get to apply low-level drivers for this hardware, adapt examples as required and test them with a debugger. Numerous exercises make this training a practical software workshop . YOUR BENEFIT: Efficient and compact jump-start into the overall topic // Practical tips on multicore and safety // Exercises on USB stick or as download.

Hardware and software architects, hardware and software developers, test engineers // IMPORTANT NOTE: A valid NDA with the chip vendor is a pre-requirement to attend the course.

ANSI-C knowledge; experience in microcontroller/microprocessor system programming and architecture

Infineon AURIX™ 2G Architecture

  • Multicore architectural blocks
  • Interconnectivity
  • Consequences for software architectures

CPU Subsystem

  • Multicore instruction set extensions
  • Registers files and context switching
  • Memory protection unit (software monitoring)

Internal Connectivity

  • Crossbar and peripheral bus
  • CPU clustering
  • Performance aspects for software

Memory

  • Memory map
  • Configuration options
  • Cache and software handling
  • Types
  • Hierarchy
  • Test

Infineon Low-Level Drivers: Overview

  • Configuration structures
  • Application programming interface
  • Library distribution
  • Frameworks and demos

Ports

Exceptions and Handling

  • Traps (hardware and software)
  • Interrupts (hardware and software)
  • Vector tables
  • Broadcast software interrupts (core synchronization)
  • External interrupts

Direct Memory Access Controller DMA

  • Move engines
  • Triggering (hardware and software)
  • Advanced features (software relaxation)

Timer

  • System timer (STM)
  • General purpose timer 12 (GPT12)
  • Capture compare unit (CCU)
  • Watchdog timer (WDT)
  • Temporal protection timer (TPS, exception timer)
  • Generic timer module (GTM) - overview

Safety and Security

  • Safety measures
  • Safety management unit (SMU)
  • Protection mechanisms
  • IO monitoring
  • Hardware security module - implementation overview

Multicore Aspects

  • Startup and boost
  • Low power options
  • Communication and synchronization
  • Intrinsics usage in C/C++
  • Tool apsects (compiler, linker)
  • Debugging (AMP, SMP)

System Control

  • Reset: sources, types and consequences
  • Boot: software configuration and modes
  • Clocking
  • Emergency stop requests

Power Management System (PMS)

  • Supply generation options
  • Embedded voltage regulators
  • Standby and wakeup
  • Die temperature sensor

Synchronous and Asynchronous Standard Peripherals

  • Micro second channel (MSC)
  • Serial peripheral interface (QSPI)
  • Inter IC interface (I2C)
  • UART (ASCLIN)

Sensor Interfaces

  • SENT
  • PSI5
  • PSI5-S

Analog To Digital Converter

  • EVADC
  • EDSADC
  • Enhanced features offloading software

Automotive Interfaces: Overview

  • LIN
  • CAN
  • FlexRay®

High Speed Serial Link Interface (HSSL)

Ethernet: Overview/Demo

Debug

  • Interfaces
  • Tracing
  • Multicore aspects

Exercises

  • Numerous exercises will be conducted on an Infineon AURIX™ board, covering the following aspects: use of low-level drivers, protection mechanisms, interrupt controller, DMA controller, system timer, port, multicore aspects, monitoring, performance measurement etc.

---------------------------------------------------------------------------

IMPORTANT NOTE: A valid NDA with the chip vendor is a pre-requirement to attend the course.

--------------------------------------------------------------------------

Please note that this training does not explicitly cover ADAS specific blocks. If required, please contact our service office prior to the training, phone +49 (0)89 450617-71.


The price includes lunch,

drinks, training documentation and training certificate.


Information for HR

You can book up to 5 participants on one training with our online order form.
If you wish to book more participants on several trainings, please contact us!
Please also note our bonus program when booking several trainings and/or participants at once.


Information for HR

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Tracing and Multicore Debugging with the PLS Universal Debug Engine UDE
Training Code: E-MCDS-PLS

Debugging for TriCore/AURIX™ with Lauterbach TRACE32
Training Code: E-T32-BASE

Embedded C Training: Programming Methods and Tools for Embedded Applications
Training Code: E-EMB-C

Embedded C++: Object-oriented Programming for Microcontrollers with C++/EC++ and UML
Training Code: E-EC++

Software Architectures for Embedded Systems and Real-Time Systems
Training Code: E-EMB-ARCH

Embedded Multicore Microcontrollers: Practical Application
Training Code: E-µC-MULTI


Related trainings

Trainings

The trainings marked with are guaranteed to be held.

DatePrice *Duration
04.06. – 08.06.20182.750,00 €4.5 days
10.09. – 14.09.20182.750,00 €5 days 
26.11. – 30.11.20182.750,00 €5 days 
04.02. – 08.02.20192.750,00 €5 days 
Training code: E-AURIX-2G
* All prices are exclusive of applicable VAT.


> Registration form download (PDF)
> Training details as PDF

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In customized workshops, we integrate your specific project tasks and our training program, considering your requirements as regards content, time, location, duration, technical environment and knowledge transfer methodology.

Please contact us for further information or an individual quotation.

> Training details as PDF

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AURIX™ TC3xx Workshop: 32-Bit Multicore Microcontroller Family (2G Second Generation)

Content

Infineon AURIX™ 2G Architecture

  • Multicore architectural blocks
  • Interconnectivity
  • Consequences for software architectures

CPU Subsystem

  • Multicore instruction set extensions
  • Registers files and context switching
  • Memory protection unit (software monitoring)

Internal Connectivity

  • Crossbar and peripheral bus
  • CPU clustering
  • Performance aspects for software

Memory

  • Memory map
  • Configuration options
  • Cache and software handling
  • Types
  • Hierarchy
  • Test

Infineon Low-Level Drivers: Overview

  • Configuration structures
  • Application programming interface
  • Library distribution
  • Frameworks and demos

Ports

Exceptions and Handling

  • Traps (hardware and software)
  • Interrupts (hardware and software)
  • Vector tables
  • Broadcast software interrupts (core synchronization)
  • External interrupts

Direct Memory Access Controller DMA

  • Move engines
  • Triggering (hardware and software)
  • Advanced features (software relaxation)

Timer

  • System timer (STM)
  • General purpose timer 12 (GPT12)
  • Capture compare unit (CCU)
  • Watchdog timer (WDT)
  • Temporal protection timer (TPS, exception timer)
  • Generic timer module (GTM) - overview

Safety and Security

  • Safety measures
  • Safety management unit (SMU)
  • Protection mechanisms
  • IO monitoring
  • Hardware security module - implementation overview

Multicore Aspects

  • Startup and boost
  • Low power options
  • Communication and synchronization
  • Intrinsics usage in C/C++
  • Tool apsects (compiler, linker)
  • Debugging (AMP, SMP)

System Control

  • Reset: sources, types and consequences
  • Boot: software configuration and modes
  • Clocking
  • Emergency stop requests

Power Management System (PMS)

  • Supply generation options
  • Embedded voltage regulators
  • Standby and wakeup
  • Die temperature sensor

Synchronous and Asynchronous Standard Peripherals

  • Micro second channel (MSC)
  • Serial peripheral interface (QSPI)
  • Inter IC interface (I2C)
  • UART (ASCLIN)

Sensor Interfaces

  • SENT
  • PSI5
  • PSI5-S

Analog To Digital Converter

  • EVADC
  • EDSADC
  • Enhanced features offloading software

Automotive Interfaces: Overview

  • LIN
  • CAN
  • FlexRay®

High Speed Serial Link Interface (HSSL)

Ethernet: Overview/Demo

Debug

  • Interfaces
  • Tracing
  • Multicore aspects

Exercises

  • Numerous exercises will be conducted on an Infineon AURIX™ board, covering the following aspects: use of low-level drivers, protection mechanisms, interrupt controller, DMA controller, system timer, port, multicore aspects, monitoring, performance measurement etc.

---------------------------------------------------------------------------

IMPORTANT NOTE: A valid NDA with the chip vendor is a pre-requirement to attend the course.

--------------------------------------------------------------------------

Please note that this training does not explicitly cover ADAS specific blocks. If required, please contact our service office prior to the training, phone +49 (0)89 450617-71.

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