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Cortex®-M7, M4, M3, M1, M0: Arm® Cortex-M Architecture Training

  • Content
     
  • Objectives
     
  • Participants
     
  • Requirements
     

You know the Cortex®-M7, M4, M3, M1, M0 architecture and can write software in C and Assembler. You can place the programs in memory and test them. You get the perfect introduction in developing Cortex®-M based systems.

Hardware and software developers

A basic understanding of ANSI-C and microcontrollers.

Cortex®-M (Armv7-M, Armv6-M) Processor Architecture

  • Register organization, special purpose register
  • Operation modes (handler/thread, privileged/unprivileged)
  • Main stack, process stack
  • Cortex®-M pipeline concept
  • Cortex®-M memory map, system control block, bit banding

Arm Processor Cores - Overview

  • Cortex®-M, Cortex®-R, Cortex®-A
  • Arm7/9/10/11

Cortex®-M7, M4, M3, M1, M0 Instruction Set

  • Thumb-2 instruction set
  • Data processing instructions
  • Branch and control flow instructions, subroutines
  • Branch table, if ... then conditional blocks
  • Data access instructions
  • Assembler directives

Exception and Interrupt Handling

  • Exception model
  • Reset, NMI, faults, SysTick, debug, supervisor calls, external interrupts
  • Tail chaining, late arriving
  • Nested vector interrupt controller (NVIC)
  • Interrupt configuration and status
  • Interrupt prioritization, priority grouping

Reset Modes, Clock Generation, Power Management

  • Clock generation
  • Resets and Cortex®-M reset modes
  • Power management
  • System timer

Memory Interface

  • Bus interfaces for: AMBA 3 Bus, instruction/data memories
  • System interface, external private peripherals

Memory Protection Unit MPU for Embedded Systems

Cache, Tightly Coupled Memory (TCM)

Embedded Core Debugging

  • Core and system debugging
  • JTAG debug port
  • 2-pin single wire debug port
  • Trace port interface unit
  • Embedded trace macrocell

Embedded Software Development

  • Adjustment of library routines to hardware (retargeting)
  • Placing code and data in memory (scatter loading)
  • Linker description files
  • Processor start-up, start-up file
  • Tools: Arm, IAR, GNU

Efficient C-Programming for Cortex Architectures

  • Compiler optimization, compiler options
  • Interface C - Assembler
  • Programming guidelines for Cortex compilers
  • Optimized utilization of local and global data
  • Tools: Arm, IAR, GNU

Hardware-near C-Programming According to CMSIS

  • Cortex Microcontroller Software Interface Standard (CMSIS)
  • Software architecture for embedded systems
  • Structured description of peripherals
  • Access to peripherals in C
  • C statements and their execution in Assembler

Floating Point Unit, Digital Signal Processing

Practical Exercises with IAR Workbench, Atmel Studio 6 & ASF or Keil µVision and ARM RealView Tools

  • Exercises - key elements of the Cortex®-M4, M3, M1, M0 architecture
  • All programs are tested on a Cortex-M based evaluation board
  • Cortex®-M4: Freescale Kinetis Arm Cortex®-M4 microcontrollers
  • Atmel SAM4S EK2 Cortex®-M4 evaluation kit
  • Cortex®-M4: Atmel SAM4S Xplained Cortex®-M4 evaluation kit
  • Cortex®-M3: NXP LPC1700 family
  • STMicroelectronics STM32 family
  • Cortex®-M3: Spansion FM3 family
  • Cortex®-M4: Spansion FM4 family
  • Cortex®-M0: Nuvoton NuMicro™ family
  • Alternative tools can be used on request

EXTRA: Participants get a FREE Atmel SAM4S Xplained Cortex-M4 evaluation kit.

The training price includes:
Lunch, drinks, training documentation and your training certificate.


ALL INCLUSIVE!



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Related trainings

Trainings

DatePrice *Duration
09.03. – 12.03.20202.400,00 €4 days 
Training code: E-CORTEXMX
* Price per attendee, in Euro plus VAT


> Registration form download (PDF)
> Training details as PDF

Onsite Training

Our customized workshops integrate your specific project tasks in our training content and accommodate your requirements on content, time, location, duration, technical environment and knowledge transfer methodology.

Please contact us for further information or an individual quotation.

> Training details as PDF

Coaching

Our coaching services offer a major advantage: our specialists introduce their expertise and experience directly in your solution process, thus contributing to the success of your projects.

Coaching: Arm®/CORTEX®

Cortex®-M7, M4, M3, M1, M0: Arm® Cortex-M Architecture Training

Content

Cortex®-M (Armv7-M, Armv6-M) Processor Architecture

  • Register organization, special purpose register
  • Operation modes (handler/thread, privileged/unprivileged)
  • Main stack, process stack
  • Cortex®-M pipeline concept
  • Cortex®-M memory map, system control block, bit banding

Arm Processor Cores - Overview

  • Cortex®-M, Cortex®-R, Cortex®-A
  • Arm7/9/10/11

Cortex®-M7, M4, M3, M1, M0 Instruction Set

  • Thumb-2 instruction set
  • Data processing instructions
  • Branch and control flow instructions, subroutines
  • Branch table, if ... then conditional blocks
  • Data access instructions
  • Assembler directives

Exception and Interrupt Handling

  • Exception model
  • Reset, NMI, faults, SysTick, debug, supervisor calls, external interrupts
  • Tail chaining, late arriving
  • Nested vector interrupt controller (NVIC)
  • Interrupt configuration and status
  • Interrupt prioritization, priority grouping

Reset Modes, Clock Generation, Power Management

  • Clock generation
  • Resets and Cortex®-M reset modes
  • Power management
  • System timer

Memory Interface

  • Bus interfaces for: AMBA 3 Bus, instruction/data memories
  • System interface, external private peripherals

Memory Protection Unit MPU for Embedded Systems

Cache, Tightly Coupled Memory (TCM)

Embedded Core Debugging

  • Core and system debugging
  • JTAG debug port
  • 2-pin single wire debug port
  • Trace port interface unit
  • Embedded trace macrocell

Embedded Software Development

  • Adjustment of library routines to hardware (retargeting)
  • Placing code and data in memory (scatter loading)
  • Linker description files
  • Processor start-up, start-up file
  • Tools: Arm, IAR, GNU

Efficient C-Programming for Cortex Architectures

  • Compiler optimization, compiler options
  • Interface C - Assembler
  • Programming guidelines for Cortex compilers
  • Optimized utilization of local and global data
  • Tools: Arm, IAR, GNU

Hardware-near C-Programming According to CMSIS

  • Cortex Microcontroller Software Interface Standard (CMSIS)
  • Software architecture for embedded systems
  • Structured description of peripherals
  • Access to peripherals in C
  • C statements and their execution in Assembler

Floating Point Unit, Digital Signal Processing

Practical Exercises with IAR Workbench, Atmel Studio 6 & ASF or Keil µVision and ARM RealView Tools

  • Exercises - key elements of the Cortex®-M4, M3, M1, M0 architecture
  • All programs are tested on a Cortex-M based evaluation board
  • Cortex®-M4: Freescale Kinetis Arm Cortex®-M4 microcontrollers
  • Atmel SAM4S EK2 Cortex®-M4 evaluation kit
  • Cortex®-M4: Atmel SAM4S Xplained Cortex®-M4 evaluation kit
  • Cortex®-M3: NXP LPC1700 family
  • STMicroelectronics STM32 family
  • Cortex®-M3: Spansion FM3 family
  • Cortex®-M4: Spansion FM4 family
  • Cortex®-M0: Nuvoton NuMicro™ family
  • Alternative tools can be used on request

EXTRA: Participants get a FREE Atmel SAM4S Xplained Cortex-M4 evaluation kit.

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