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TC17x7: Practical Application of TriCore™ Specific Peripherals - Face-to-Face Training

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  • Objectives
     
  • Participants
     
  • Requirements
     

You can assess the possible applications of TriCore™ specific peripherals of the TC17x6/TC17x7 derivatives. You are able to generate driver routines, implement these in a project and test them with a debugger. You understand the interaction between the peripherals and the service platforms (CPU/PCP service or DMA transfer).

Hardware and software architects, hardware and software developers, test engineers

Basic knowledge of microcontrollers and the TriCore™ architecture as covered in the training "TriCore™: Architecture, Peripherals and Embedded Programming".

TriCore™ Overview

  • Core, bus systems, port structure

Peripheral Control Processor PCP2

  • PCP2 configuration, channel programs and contexts
  • Instruction set overview
  • PCP2 service request nodes and service request structure
  • PCP2 interruptible channel programs

General Purpose Timer Array GPTA V4/V5

  • Clock generation unit
  • Filter prescaler cells FPCs, phase discrimination logic PDLs
  • Duty cycle measurement DCMs, phase locked loop PLL
  • Clock distribution unit CDU
  • Signal generation unit (global timer GTs, global timer cells GTCs, local timer cells LTCs)
  • GPTA input/output and interrupt/DMA interface

Micro Second Channel MSCx

  • Downstream channel
  • Upstream channel

A/D Converter ADCx (TC17x6/TC17x7)

  • Request sources and arbitration
  • Conversion and sample time control, limit check
  • Service request control

Fast A/D Converter FADC

  • Channel trigger/gate control, data reduction filter block

Direct Memory Access Controller DMA, Memory Checker

  • Architecture, initialization, interrupt handling
  • Addressing mechanisms, protection handling, pattern detection logic

External Request Unit ERU

Micro Link Interfaces MLIx

  • Communication process, transfer windows, pipes, transfer formats

MultiCAN Module

  • CAN node initialization and message object handling
  • FIFO/Gateway architecture and handling
  • CAN interrupt handling

FlexRay Module TC1797 (Overview)

The training price includes:
Lunch, drinks, training documentation and your training certificate.


ALL INCLUSIVE!

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FACE-TO-FACE TRAINING

Price *Duration
-3 days
Training code: E-TC17XXP
* Price per attendee, in Euro plus VAT
> Registration form download (PDF)> Training details as PDF

Onsite Training

Our customized workshops integrate your specific project tasks in our training content and accommodate your requirements on content, time, location, duration, technical environment and knowledge transfer methodology.

Please contact us for further information or an individual quotation.

> Training details as PDF

Face-To-Face - German

Duration
3 days  

Coaching

Our coaching services offer a major advantage: our specialists introduce their expertise and experience directly in your solution process, thus contributing to the success of your projects.

We will be happy to provide you with further information or submit a quotation tailored to your requirements.

TC17x7: Practical Application of TriCore™ Specific Peripherals - Face-to-Face Training

Content

TriCore™ Overview

  • Core, bus systems, port structure

Peripheral Control Processor PCP2

  • PCP2 configuration, channel programs and contexts
  • Instruction set overview
  • PCP2 service request nodes and service request structure
  • PCP2 interruptible channel programs

General Purpose Timer Array GPTA V4/V5

  • Clock generation unit
  • Filter prescaler cells FPCs, phase discrimination logic PDLs
  • Duty cycle measurement DCMs, phase locked loop PLL
  • Clock distribution unit CDU
  • Signal generation unit (global timer GTs, global timer cells GTCs, local timer cells LTCs)
  • GPTA input/output and interrupt/DMA interface

Micro Second Channel MSCx

  • Downstream channel
  • Upstream channel

A/D Converter ADCx (TC17x6/TC17x7)

  • Request sources and arbitration
  • Conversion and sample time control, limit check
  • Service request control

Fast A/D Converter FADC

  • Channel trigger/gate control, data reduction filter block

Direct Memory Access Controller DMA, Memory Checker

  • Architecture, initialization, interrupt handling
  • Addressing mechanisms, protection handling, pattern detection logic

External Request Unit ERU

Micro Link Interfaces MLIx

  • Communication process, transfer windows, pipes, transfer formats

MultiCAN Module

  • CAN node initialization and message object handling
  • FIFO/Gateway architecture and handling
  • CAN interrupt handling

FlexRay Module TC1797 (Overview)