SPC56XX: 32-Bit Single-Core Power Architecture®
You know the Power Architecture with the SOC implementation of STMicroelectronics, the on-chip peripherals (basic and special peripheral modules) and features of the SPC56x family. You are able to program low-level drivers for this hardware and test them with a debugger. Moreover, you can generate routines for DMA, interrupts and exceptions.
Hardware and software architects, hardware and software developers, test engineers
Knowledge of ANSI-C as well as experience with programming a microcontroller architecture. Knowledge of DSP is an advantage.
STMicroelectronics SPC56x Architecture: Overview
Power Architecture (e200z0h) Overview
- CPU, pipeline, register sets
- Memory model
- Memory units: SRAM, flash memory
Overview: Instruction Set
On-chip Bus Systems
- Multi-layer AHB crossbar switch XBAR
- Peripheral bridge, peripheral bus
Interrupt and Exception Handling: Vector Table and Service Routines
- Interrupt controller INTC
Direct Memory Access Controller DMA
SPC56x On-chip Peripherals:
- Software watchdog timer module SWT
- System timer module STM
- Periodic interrupt timer PIT
- Real-time clock module RTC
- FlexPWM unit
- Enhanced timer eTimer
- Enhanced modular IO subsystem eMIOS
Cross Triggering Unit CTU
Analog-Digital Signal Processing
- 10 bit /12 bit analog-digital converter ADC
- Deserial / serial peripheral interface DSPI
- Enhanced serial communication interface eSCI / LINFlex
- Safety port
System Integration Unit Lite SIUL
Fault Collection Unit FCU
- Reset configuration, monitoring and generation
- Clock generation: FMPLL, internal oscillator
- External interrupts
- GPIO (pin definition and port functions)
- External multiplexing (e.g. ADC, DSPIs)
- Start-up process
- Boot assist module BAM
Power Management Controller PMC
- JTAG controller JTAG, Nexus2+ interface
- Exercises are performed with an SPC56x starter kit, focusing on the aspects interrupt controller, DMA controller, basic peripheral modules.
OPEN FACE-TO-FACE FORMAT
|Training code: E-SPC56XX|
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