Infineon TRAVEO™ T2G Online Training for Automotive Body Control
32-bit TRAVEO™ T2G Microcontroller based on Arm® for automotive body electronics applications offers cutting-edge performance, safety and security features.
Thanks to its special features, the TRAVEO™ T2G family is the perfect match for connected cars.
With processing power scalable from single Arm® Cortex®-M4F to dual Cortex®-M7F and its network connectivity, the TRAVEO™ T2G family comes up with an enhanced performance of up to 1500 DMIPS and a high-performance CPU operating up to 350 MHz.
Infineon TRAVEO™ T2G Online Training
The TRAVEO™ T2G Body microcontroller series is targeted at automotive systems such as seat control units with low current consumption requirements. These devices have either an Arm® Cortex®-M4 CPU or up to two Arm® Cortex®-M7 CPUs for primary processing and a Cortex-M0+ CPU for peripheral and security processing. The TRAVEO™ T2G devices contain embedded peripherals supporting Controller Area Network with Flexible Data rate (CAN FD), Local Interconnect Network (LIN), Gigabit Ethernet, FlexRay and Clock Extension Peripheral Interface (CXPI). Network connectivity, the intelligent link between PWM control and the three simultaneously triggerable ADC units make TRAVEO™ T2G a perfect match for 3-phase motor control.
TRAVEO™ T2G is manufactured on an advanced 40nm process. It incorporates Infineon's low-power flash memory, multiple high-performance analog and digital peripherals, and enables the creation of a secure computing platform.
The previous brand name TRAVEO™ II has been replaced with TRAVEO™ T2G; however, both names may be used as synonyms.
We have developed an Online Learning format for you to get started with the Infineon TRAVEO™ T2G family:
In this Online Training, you improve your basic knowledge and learn how to develop TRAVEO™ T2G based body control applications and perform exercises on your Infineon TRAVEO™ T2G starter Kit CYTVII-B-E-1M-SK. The training highlights the CPU subsystem with Arm Cortex-M, exceptions, interrupt priorities, MPU settings and the peripheral subsystem comprising several complex communication interfaces - both in theory and in a series of practical exercises.
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