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ARMv8-M Architecture (Cortex™-M23/-M33) Online Training - for Participants with Knowledge of the Previous Architecture

In this Online Training, you get familiar with the new ARMv8-M architecture (Cortex™-M23 and -M33) and can write software in C and Assembler. You can locate programs in memory in secure and non secure configuration and test them. This is the perfect start for designing Cortex™-M23/M33 based systems.

After successfully taking part in the seminar and performing the related excercises, you will be granted the MicroConsult Training Certificate.



  • Content
     
  • Objectives
  • Participants
  • Requirements

You know the new ARMv8-M architecture (Cortex™-M23 and -M33) and can write software in C and Assembler. You can locate programs in memory in secure and non secure configuration and test them. This is the perfect start for designing Cortex™-M23/M33 based systems.

Your trainer: Dipl.-Ing. Remo Markgraf.

The ARMv8-M Architecture Update Online Training addresses software and hardware developers with a basic knowledge of the previous architecture (ARMv6-M/ ARMv7-M architecture of the Cortex™-M0/M0+/M3/M4 or -M7).

Basic knowledge of the ARMv6-M/ ARMv7-M architecture of the Cortex™-M0/M0+/M3/M4 or -M7 is required, as well as basic knowledge of ANSI-C and microcontrollers.

The taining focuses on the new features offered by the Cortex™-M23, M33 and the ARMv8-M architecture.

TrustZone for ARMv8-M

  • Secure state transitions
  • Function calls from secure state to non-secure state
  • Function returns from non-secure state
  • Practical exercises: developing and setting up mixed secure/non-secure projects for Cortex-M33


Cortex™-M (ARMv8-M) Processor Architecture

  • Stack limit register
  • Secure state, security transitions
  • Banked registers
  • Cortex™-M memory map, system control block
  • Practical exercises: New stack limit registers


Differences to the ARMv6-M and ARMv7-M Processor Architecture

Cortex™-M33, M23 Extended Instruction Set

  • Branch and control flow instructions with security transitions
  • Security instructions
  • Assembler directives
  • Practical exercises: Generating Assembler routines, Assembler debugging, code optimizaiton

Exception and Interrupt Handling

  • Security targeting
  • Banked exceptions
  • Banked vector tables
  • Tail chaining with security transitions
  • Interrupt configuration and status
  • Secure exception priority boosting
  • Secure faults
  • Practical exercises: System tick, supervisor call and PendSV in the context of RTOS applications
  • Practical exercises: Fault handlers and status information output


Memory Protection Unit MPU for Embedded Systems

  • ARMv8-M MPU
  • Comparision to previous ARMv7-M MPU
  • Practical exercises: Programming the MPU
  • Practical exercises: Dynamic reprogramming in the scheduler


Security Attribution Unit (SAU, IDAU)

  • Overview on the security and implementation defined attribution unit
  • Attribution attributes secure, non-secure, non-secure callable
  • Practical exercises: Programming the security attribution unit


Hardware-near C Programming based on CMSIS

  • CMSIS extensions for ARMv8-M


Exercises with Keil µVision in Assembler and C

  • Exercises for ARMv8-M are performed with the ARM Simulator

This online training will be available soon.



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