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Cortex®-M23, M33: Armv8-M Architecture Training for Trainees with Knowledge of the Previous Version - Online Training

In this Online Training, you get familiar with the new Arm®v8-M architecture (Cortex®-M23 and -M33) and can write software in C and Assembler. You can locate programs in memory in secure and non secure configuration and test them. This is the perfect start for designing Cortex®-M23/M33 based systems.

After successfully taking part in the seminar and performing the related exercises, you will be granted the MicroConsult Training Certificate.


  • Content
     
  • Objectives
     
  • Participants
     
  • Requirements
     

You know the new Armv8-M architecture (Cortex®-M23 and -M33) and can write software in C and Assembler. You can locate programs in memory in secure and non secure configuration and test them. This is the perfect start for designing Cortex®-M23/M33 based systems.

Your trainer: Dipl.-Ing. Remo Markgraf.

The Armv8-M Architecture Update Online Training addresses software and hardware developers with a basic knowledge of the previous architecture (Armv6-M/ Armv7-M architecture of the Cortex®-M0/M0+/M3/M4 or -M7).

Basic knowledge of the Armv6-M/ Armv7-M architecture of the Cortex®-M0/M0+/M3/M4 or -M7 as well as basic knowledge of ANSI-C and microcontrollers is required.

The training focuses on the new features offered by the Cortex®-M23, M33 and the Armv8-M architecture.

TrustZone for Armv8-M

  • Secure state transitions
  • Function calls from secure state to non-secure state
  • Function returns from non-secure state
  • Practical exercises: Developing and setting up mixed secure/non-secure projects for Cortex®-M33


Cortex®-M (Armv8-M) Processor Architecture

  • Stack limit register
  • Secure state, security transitions
  • Banked registers
  • Cortex™-M memory map, system control block
  • Practical exercises: New stack limit registers


Differences to the Armv6-M and Armv7-M Processor Architecture

Cortex®-M33, M23 Extended Instruction Set

  • Branch and control flow instructions with security transitions
  • Security instructions
  • Assembler directives
  • Practical exercises: Generating Assembler routines, Assembler debugging, code optimization

Exception and Interrupt Handling

  • Security targeting
  • Banked exceptions
  • Banked vector tables
  • Tail chaining with security transitions
  • Interrupt configuration and status
  • Secure exception priority boosting
  • Secure faults
  • Practical exercises: System tick, supervisor call and PendSV in the context of RTOS applications
  • Practical exercises: Fault handlers and status information output


Memory Protection Unit MPU for Embedded Systems

  • Armv8-M MPU
  • Comparison to previous Armv7-M MPU
  • Practical exercises: Programming the MPU
  • Practical exercises: Dynamic reprogramming in the scheduler


Security Attribution Unit (SAU, IDAU)

  • Overview on the security and implementation defined attribution unit
  • Attribution attributes secure, non-secure, non-secure callable
  • Practical exercises: Programming the security attribution unit


Hardware-near C Programming based on CMSIS

  • CMSIS extensions for Armv8-M


Exercises with Keil µVision in Assembler and C

  • Exercises for Armv8-M are performed with the Arm Simulator

 

NOTE: As an alternative to this online training, you may wish to learn about this architecture in more detail and take part in our attendance training:

 

This online training will be available soon.


ALTERNATIVE - Attendance Training:
Cortex®-M23, M33: Armv8-M Architecture for Trainees with Knowledge of the Previous Version



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