Experience Embedded

Professional Training, Consulting and Project Support

Cortex™-A5, A7, A8, A9, A15, A17: ARM Cortex-A Architecture Training

  • Content
     
  • Objectives
  • Participants
  • Requirements

You know the Cortex™-A architecture and can write software in C and Assembler. This is the perfect start for designing ARM based systems.

Software and hardware developers

A basic understanding of ANSI-C and microcontrollers.

Cortex™-Ax Processor Architecture

  • Operating modes, states, pipeline, register organization
  • User mode, fast interrupt (FIQ) mode, interrupt (IRQ) mode
  • Supervisor mode, system mode, undefined mode, secure monitor mode
  • Thumb-2 state, ARM state, Jazelle state, ThumbEE state
  • Cortex™-Ax register file
  • Status register

ARM Processor Cores: Overview

  • Cortex™-M, Cortex™-R, Cortex™-A processor cores
  • ARM7 / ARM9 / ARM10 / ARM11

ARM, Thumb-2 and DSP Instruction Sets

  • v7 Thumb-2 instruction set
  • ARM/Thumb interworking
  • Most important assembler directives
  • v4, v4T, v5, v6 instruction set overview

Advanced SIMD and VFP Extension

  • NEON coprocessor
  • VFP floating point unit

Jazelle RCT Extension Overview

  • Thumb-2EE instruction set
  • ThumbEE state

Exception Handling

  • Exception modes: FIQ, IRQ, ABORT, UNDEF, SVC, SMC
  • Exception handler templates
  • Vector tables: normal, secure, monitor mode
  • TrustZone (secure) exception handling
  • Exception handling in singlecore and multicore systems
  • Global interrupt controller (GIC)
  • Vector interrupt controller (VIC)

System Control Coprocessor, CP15

  • ARM coprocessor concept, CP0 ... CP15
  • Overall system control & configuration
  • Cache configuration and cache management
  • Memory management unit (MMU) configuration
  • System performance monitoring (PMU)

Level 1 Memory System

  • Instruction and data cache
  • Cache initialization
  • Store buffer

Level 2 Memory System

  • Advanced microprocessor bus architecture (AXI)
  • AXI bus masters
  • AXI bus slaves
  • Second level caches
  • Preload engine (PLE)
  • On-chip RAM and flash, peripherals
  • External memory interface (EMI)

Memory Management Unit MMU

  • Translation lookaside buffer (TLB)
  • Translation and page tables, attributes
  • Virtual addressing, tablewalk

Cortex™-Ax Multiprocessor Core

  • Primary, secondary CPU
  • Global interrupt controller (GIC)
  • Snoop control unit (SCU)
  • Accelerator coherency port (ACP)
  • Address filtering

Startup Singlecore System

  • Startup file
  • Vector table, stack, PLL and data initialization
  • Cache, MMU and branch predictor initialization
  • From reset to main

Startup Multicore System

  • From reset to main
  • Primary CPU initialization
  • Secondary CPU initialization

Clock, Reset and Power Control

  • Low power modes

TrustZone Extension

  • TrustZone overview
  • Secure monitor mode
  • TrustZone exception handling
  • Startup in Secure world
  • Switch from Secure world to Non-secure world

Virtualization Extension

  • Hyp mode
  • Hypervisor
  • Large address extension
  • L1 and L2 tablewalk

Cortex™-Ax Debug Support

  • Embedded trace macrocell (ETM)
  • Program trace macrocell (PTM)
  • CoreSight debug components
  • Performance monitoring unit (PMU)
  • Cross trigger unit
  • Debug coprocessor, CP14

Software Development Overview

  • Compiler options
  • Linker options
  • Description file
  • Locating program and data in memory

Practical exercises on all topics with IAR Workbench and an evaluation board


The price includes lunch,

drinks, training documentation and certificate.


Information for HR

You can book up to 5 participants on one training with our online order form.
If you wish to book more participants on several trainings, please contact us!
Please also note our bonus program when booking several trainings and/or participants at once.


Information for HR

Related trainings

Cortex™-A5, A7, A8, A9, A15, A17: ARM Cortex-A Architektur Training
Training Code: CORTEX-AX

Cortex™-R4: ARM Cortex-R Architecture Training
Training Code: E-CORTEXR4

STM32: Technical Training
Training Code: E-STM32

XMC4000 / XCM1000 Workshop: 32-Bit Industrial Microcontroller ARM® Cortex™-M4/ ARM® Cortex™-M0
Training Code: E-XMC4000

ARM7/ ARM9/ ARM10/ ARM11™: Architecture and Embedded Programming
Training Code: E-ARM-7/9

Embedded C Training: Programming Methods and Tools for Embedded Applications
Training Code: E-EMB-C

Embedded C++: Object-oriented Programming for Microcontrollers with C++/EC++ and UML
Training Code: E-EC++

Atmel Studio 6 & ASF: Application for Atmel ARM Core-based Flash Microcontrollers
Training Code: E-ATMEL-S


Related trainings

Trainings

DatePrice *Duration
05.03. – 08.03.20182.200,00 €4 days 
25.06. – 28.06.20182.200,00 €4 days 
12.11. – 15.11.20182.200,00 €4 days 
11.03. – 14.03.20192.200,00 €4 days 
Training code: E-CORTEXAX
* All prices are exclusive of applicable VAT.


> Registration form download (PDF)
> Training details as PDF

Inhouse Training

In customized workshops, we integrate your specific project tasks and our training program, considering your requirements as regards content, time, location, duration, technical environment and knowledge transfer methodology.

Please contact us for further information or an individual quotation.

> Training details as PDF

Coaching

Unsere Coaching-Angebote bieten den großen Vorteil, dass unsere Experten ihr Wissen und ihre Erfahrungen direkt in Ihren Lösungsprozess einbringen und damit unmittelbar zu Ihrem Projekterfolg beitragen.

Für Ihre Anfrage oder weiterführende Informationen stehen wir Ihnen gern zur Verfügung.

Cortex™-A5, A7, A8, A9, A15, A17: ARM Cortex-A Architecture Training

Content

Cortex™-Ax Processor Architecture

  • Operating modes, states, pipeline, register organization
  • User mode, fast interrupt (FIQ) mode, interrupt (IRQ) mode
  • Supervisor mode, system mode, undefined mode, secure monitor mode
  • Thumb-2 state, ARM state, Jazelle state, ThumbEE state
  • Cortex™-Ax register file
  • Status register

ARM Processor Cores: Overview

  • Cortex™-M, Cortex™-R, Cortex™-A processor cores
  • ARM7 / ARM9 / ARM10 / ARM11

ARM, Thumb-2 and DSP Instruction Sets

  • v7 Thumb-2 instruction set
  • ARM/Thumb interworking
  • Most important assembler directives
  • v4, v4T, v5, v6 instruction set overview

Advanced SIMD and VFP Extension

  • NEON coprocessor
  • VFP floating point unit

Jazelle RCT Extension Overview

  • Thumb-2EE instruction set
  • ThumbEE state

Exception Handling

  • Exception modes: FIQ, IRQ, ABORT, UNDEF, SVC, SMC
  • Exception handler templates
  • Vector tables: normal, secure, monitor mode
  • TrustZone (secure) exception handling
  • Exception handling in singlecore and multicore systems
  • Global interrupt controller (GIC)
  • Vector interrupt controller (VIC)

System Control Coprocessor, CP15

  • ARM coprocessor concept, CP0 ... CP15
  • Overall system control & configuration
  • Cache configuration and cache management
  • Memory management unit (MMU) configuration
  • System performance monitoring (PMU)

Level 1 Memory System

  • Instruction and data cache
  • Cache initialization
  • Store buffer

Level 2 Memory System

  • Advanced microprocessor bus architecture (AXI)
  • AXI bus masters
  • AXI bus slaves
  • Second level caches
  • Preload engine (PLE)
  • On-chip RAM and flash, peripherals
  • External memory interface (EMI)

Memory Management Unit MMU

  • Translation lookaside buffer (TLB)
  • Translation and page tables, attributes
  • Virtual addressing, tablewalk

Cortex™-Ax Multiprocessor Core

  • Primary, secondary CPU
  • Global interrupt controller (GIC)
  • Snoop control unit (SCU)
  • Accelerator coherency port (ACP)
  • Address filtering

Startup Singlecore System

  • Startup file
  • Vector table, stack, PLL and data initialization
  • Cache, MMU and branch predictor initialization
  • From reset to main

Startup Multicore System

  • From reset to main
  • Primary CPU initialization
  • Secondary CPU initialization

Clock, Reset and Power Control

  • Low power modes

TrustZone Extension

  • TrustZone overview
  • Secure monitor mode
  • TrustZone exception handling
  • Startup in Secure world
  • Switch from Secure world to Non-secure world

Virtualization Extension

  • Hyp mode
  • Hypervisor
  • Large address extension
  • L1 and L2 tablewalk

Cortex™-Ax Debug Support

  • Embedded trace macrocell (ETM)
  • Program trace macrocell (PTM)
  • CoreSight debug components
  • Performance monitoring unit (PMU)
  • Cross trigger unit
  • Debug coprocessor, CP14

Software Development Overview

  • Compiler options
  • Linker options
  • Description file
  • Locating program and data in memory

Practical exercises on all topics with IAR Workbench and an evaluation board

Wishlist


No trainings